The present invention relates generally to semiconductor fabrication, and more specifically, to a structure and method of fabricating a vertical heterojunction tunnel field effect transistor (TFET) using limited lithography steps.
Heterojunction TFET devices typically require asymmetric source/drain regions (i.e, opposite conductivity types), which are difficult to fabricate using conventional processes. Conventional heterojunction TFET fabrication techniques involve lithography processes that require the deposition, patterning, and removal of at least two different photoresist layers during the fabrication process. For example, a first lithography may occur prior to formation of the heterojunction TFET's source region. A second lithography may occur after the source region is formed but prior to the formation of an oppositely doped drain region.
Each incidence of the lithography process, including the photoresist deposition, patterning and etching processes associated with it, may subject semiconductor devices located on the semiconductor substrate to harsh processing conditions. This may result in a reduced yield of quality wafers from each manufactured batch and subsequent performance issues. Each lithography incidence may also increase the time duration and cost associated with the heterojunction TFET fabrication process.